1. Field of the Invention
The present invention relates in general to computer hardware, and, more particularly, to a static random access memory (SRAM).
2. Description of Related Art
FIG. 1 shows a schematic diagram of the layout of a prior art SRAM device 100. SRAM device 100 consists of two cell arrays 101. Each array 101 comprises 32 columns and 512 rows of SRAM cells 102. For each column of cells in each cell array, SRAM device 100 also has a set of column support circuitry 104 which is stacked immediate below the cell array. Analogously, for each row of cells in each cell array, SRAM device 100 has a set of row support circuitry 106. Those skilled in the art will understand that the row and column support circuitry include word-line drivers, address latches, decoders, sense amps, data input latches, data output latches, write drivers, and other components needed to access the array of cells.
FIG. 1A is a schematic diagram of the architecture of each SRAM cell 102 of FIG. 1. As shown in FIG. 1A, each SRAM cell 102 comprises six transistors: two cross-coupled inverters 150 and 155 as a latch element and two access transistors 142, 144 for reading and writing. Word-line 105 travels horizontally controlling N-channel access transistors 142 and 144. N-channel transistors 142 and 144 connect the interior or latch portion of the SRAM cell 102 to a vertical bit-line true 110 and a vertical bit-line complement 115 respectively. Bit-lines 110 and 115 facilitate communication between various SRAM cells 102 of SRAM device 100. Word-line 105 runs horizontally across each row of SRAM cells 102 and facilitates communication between SRAM device 100 and external devices.
Data bits are written into individual SRAM cells 102 of a word in parallel, by activating word-line 105 corresponding to the appropriate row and pulsing appropriate bit-lines 110 or 115. Pulsing bitline 110 stores a 1 in the corresponding cell, while pulsing bit-line 115 stores a 0. Similarly data bits are read from individual SRAM cells 102 in a word in parallel, by activating word-line 105 corresponding to the appropriate row. Each cell in that row will then drive either bit-line 110 or bit-line 115 depending on the value stored in SRAM cell 102. If the stored bit value is 1, then SRAM cell 102 will drive bit-line 110, otherwise SRAM cell 102 will drive bit-line 115 indicating a stored bit value of 0.
SRAM cell 102 further comprises two cross-coupled inverters 150 and 155. Inverter 150 comprises a P-channel transistor 151 and an N-channel transistor 153. Inverter 155 comprises a P-channel channel transistor 156 and an N-channel transistor 158. The two cross-coupling nodes are node 123 and node 125. Node 123 connects N-channel transistor 142 with the common node of inverter 150 and the gate node of inverter 155. The other cross-coupling node 125 connects N-channel transistor 144 with the common node of inverter 155 and the gate node of inverter 150.
One conventional layout 200 used for SRAM cell 102 is illustrated in FIG. 2 in which four mesas 232, 234, 236, and 238 contain P-channel transistors P1 (151 in FIG. 1) and P2 (156), and N-channel transistors N1 (142), N2 (153), N3 (158), and N4 (144). Mesa 232 comprises N1 and N2, mesa 234 comprises N3 and N4, mesa 236 comprises P1, and mesa 238 comprises P2. The two cross-coupling nodes are also illustrated with the same reference numerals 123 and 125 as in FIG. 1. In FIG. 2, node 123 is for the contact portion and 123-1 and 123-2 for the subsidiary portions. Similar notation is used for the node 125.
In the layout of FIG. 2 since the transistors of the same polarity are on the same mesa, there is no problem with interference from the dopants used to form the transistors.
However, prior art SRAM cell layout 200 as shown in FIG. 2 is very limiting. SRAM cell layout 200 relies on the use of one pair of bit-lines 110, 115. When this layout is utilized in SRAM device 100 (of FIG. 1), bit-lines 110, 115 run vertically on one metal level, e.g., metal-2 level, and previously described word-line 105 runs on another metal level, e.g., metal-3 level. One word-line is required for each row of a cell array, and a pair of bit-lines are required for each column of a cell array. Irrespective of the column height, the same pair of bit-lines run vertically from the bottom of each array 101 to the top covering the full array height of 512 cells. These bit-lines are long in length resulting in high bit-line capacitance and resistance.
Another problem with conventional SRAM device 100 relates to bit-line loading. Each bit-line in SRAM device 100 has capacitance and resistance which adds delay in reading and writing data bits from and to the individual cells. The long bit-lines have increased capacitance and resistance which in turn decrease the speed of the data access. In prior art, only one pair of vertical bit-lines is used irrespective of the number of rows in the cell arrays. Thus, when SRAM device 100 has relatively a large number of rows, the long length of the bit-lines results in very high impedance which results in unacceptable low performance.
At the cell level, as shown is the layout 200 of FIG. 2, prior art SRAM cell 102 has an aspect ratio with a long vertical dimension and a short horizontal dimension. This aspect ratio does not allow for any additional vertical metal channels on the same level as the bit-lines.